Increased miniaturization of components, greater packaging density of integrated circuits (“ICs”), higher performance, and lower cost are ongoing goals of the computer industry. As new generations of IC products are released, the number of devices used to fabricate them tends to decrease due to advances in technology. Simultaneously, the functionality of these products increases.
Semiconductor package structures continue to advance toward miniaturization and thinning to increase the density of the components that are packaged therein while decreasing the sizes of the products that are made therefrom. This is in response to continually increasing demands on information and communication apparatus for ever-reduced sizes, thicknesses, and costs, along with ever-increasing performance.
These increasing requirements for miniaturization are particularly noteworthy, for example, in portable information and communication devices such as cellular phones, hands-free cellular phone headsets, personal data assistants (“PDA's”), camcorders, notebook personal computers, and so forth. All of these devices continue to be made smaller and thinner to improve their portability. Accordingly, large scale IC (“LSI”) packages that are incorporated into these devices are required to be made smaller and thinner, and the package configurations that house and protect them are required to be made smaller and thinner as well.
The electronics industry is increasing the semiconductor chip density (the number of chips mounted on a single circuit board or no-lead leadframe) that parallels the reduction in the number of components that are needed for a circuit. This results in packaging designs that are more compact, in form factors (the physical size and shape of a device) that are more compact, and in a significant increase in overall IC density.
To condense further the packaging of individual devices, packages have been developed in which more than one device can be packaged at one time at each package site. Each package site is a structure that provides mechanical support for the individual IC devices. It also provides one or more layers of interconnect lines that enable the devices to be connected electrically to surrounding circuitry. Of importance to complicated packaging designs are considerations of input/output count, heat dissipation, matching of thermal expansion between a motherboard and its attached components, cost of manufacturing, ease of integration into an automated manufacturing facility, package reliability, and easy adaptability of the package to additional packaging interfaces such as a printed circuit board (“PCB”).
In some cases, multi-chip devices can be fabricated faster and more cheaply than a corresponding single IC chip that incorporates all the same functions. Current multi-chip modules typically consist of a substrate onto which a set of separate IC chip components is directly attached onto the single substrate. Such multi-chip modules have been found to increase circuit density and miniaturization, improve signal propagation speed, reduce overall device size and weight, improve performance, and lower costs—all primary goals of the computer industry.
However, such multi-chip modules can be bulky. IC package density is determined by the area required to mount a die or module on a circuit board. One method for reducing the board size of multi-chip modules and thereby increase their effective density is to stack the die or chips vertically within the module or package.
However, current multi-chip modules can also present problems because they usually must be assembled before the component chips and chip connections can be tested. That is, because the electrical bond pads on a die are so small, it is difficult to test die before assembly onto a substrate. Thus, when die are mounted and connected individually, the die and connections can be tested individually, and only known-good-die (“KGD”) that is free of defects is then assembled into larger circuits. A fabrication process that uses KGD is therefore more reliable and less prone to assembly defects introduced due to bad die. With conventional multi-chip modules, however, the die cannot be individually identified as KGD before final assembly, leading to KGD inefficiencies and assembly process problems including yield.
In addition, current multi-chip modules may require structures which increase complexity that are needed to route signals, power, and ground to the various integrated circuits in the module. For example, the substrate may require additional routing layers, separate stacking interposers, or complex redistribution structures. Also, as multiple integrated circuits are stacked or mounted side by side on a substrate, it is increasingly difficult to ensure prior to assembly of the multiple integrated circuits thereby risking increased cost if any of the integrated circuit fails.
Thus, a need still remains for a multi-chip package system providing low cost manufacturing, improved yield, higher pin count, and thinner height for the integrated circuits. In view of the ever-increasing need to save costs and improve efficiencies, it is more and more critical that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.